Computer Weekly

Microsoft shows potential of analogue optical computing in AI

Microsoft has teamed up with Barclays on a novel approach to tackling artificial intelligence (AI) and optimisation problems based on a scalable analogue optical computer (AOC) architecture, designed ...
Hosted on MSN

New 3D-stacked memory tech seeks to dethrone HBM in AI inference — d-Matrix claims 3DIMC will be 10x faster and 10x more efficient

Memory startup d-Matrix is claiming its 3D stacked memory will be up to 10x faster and run at up to 10x greater speeds than HBM. d-Matrix's 3D digital in-memory compute (3DIMC) technology is the ...
GitHub

Design High Speed Scalable Systolic Array

This work demonstrates a well-designed and optimized hardware accelerator capable of high-performance matrix multiplication. This systolic array design for 5x5 matrix multiplication has been ...
IEEE

EMMFormer: Secure Transformer Inference with Efficient Matrix Multiplication

Abstract: Transformer has been widely applied across various domains due to its outstanding performance, driving the development of numerous application services. However, in many real-world scenarios ...
IEEE

VLSI Implementation of Pipelined PE Systolic Array-Based 3x3 Matrix Multiplication for Deep Neural Network Accelerator

Abstract: The demand for efficient, low-power, and high-speed deep neural network (DNN) accelerators has driven the need for specialized hardware architectures. This work presents the VLSI ...
Frontiers

Spike-based time-domain analog weighted-sum calculation model for extremely low power VLSI implementation of multi-layer neural networks

1 Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology, Kitakyushu, Japan 2 Research Center for Neuromorphic AI Hardware, Kyushu Institute of Technology, Kitakyushu, ...