According to SiFive, its engineers enhanced the two designs with a new co-processor interface. The technology will make it ...

About SiFive SiFive is the leading provider of processor cores, accelerators, and SoC IP to create domain-specific architecture based on the free and open RISC-V instruction set architecture.

As part of the collaboration, Fractile will integrate Andes Technology’s high-performance RISC-V vector processor with its own groundbreaking in-memory computing architecture via ACE.

The Vector Processing Unit (VPU) of the AX45MPV implements RISC-V Vector Extension (RVV) version 1.0. It. It supports configurations of up to 1024-bit vector width (VLEN) and datapath width (DLEN).

(1) A computer architecture that performs more than one operation at the same time. See multicore, multithreading, GPGPU, pipeline processing and vector processor. (2) Using multiple computers ...