While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...

“Golden” RTL code has been seen as a holy grail of IC design for many years. It promises to deliver code that is reusable in future designs. However, golden RTL is very difficult to achieve. Too many ...

Achieves up to 75 percent power savings in critical semiconductor blocks; significantly reduces development costs and design risk OLDENBURG, Germany and SAN JOSE, Calif. -- May 15, 2007 -- ChipVision ...

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...

Cadence's Joules RTL Design Studio delivers up to 5X faster register-transfer-level convergence and up to 25% improved QoR through fast, accurate, and early physical insight and guidance on improving ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced a HES-DVM™ simulation ...

SANTA CLARA, Calif. – July 7, 2004 - Tensilica, Inc. today announced that it has achieved a major design automation breakthrough – the automated design of optimized configurable processors from ...

Given the relative novelty and complexity of RISC-V RTL designs, whether you are buying a commercially supported core or downloading a popular open-source offering, there is the small but non-zero ...