EDN

FPGA-to-ASIC conversion a crucial concern

It is clear that FPGAs are great for prototyping and low-volume production. It's also clear, however, that any relatively complex mid- to high-volume design for which power consumption, component cost ...
EDN

3000-plus FPGA-to-ASIC Conversions

Don’t panic, I'm still at the Multicore Expo 2006. In fact, I'm currently listening to a very interesting presentation by picoChip (www.picochip.com. These little scamps have a chip called a picoArray ...
Semiconductor Engineering

FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools

Digital systems need clocks. Today’s designs require more from clocking schemes than ever before, and it’s likely this trend will continue. Increasing power constraints have resulted in finer-grained ...
DIGITIMES

Edge AI Demand Accelerates Shift from FPGA to ASIC for Vision Inference PGC's Design Service Turnkey Platform Helps Customers Move to ASIC and Short

As AI workloads move from cloud to edge, the volume of image and sensor data across industries is rising rapidly. Edge ...
Electronic Design

Structured ASICs Compete With, And Complement, FPGAs

Once the prototyping and beta testing is done and a system goes into production, designers often will wonder: "With the higher per-chip cost of an FPGA, why not replace the FPGA with an ASIC?" But the ...
Business Wire

BitHull Overtakes ASIC Market with New FPGA Miners

COPENHAGEN, Denmark--(BUSINESS WIRE)--BitHull S.A. ( www.BitHull.com) is pleased to announce the launch of its two new crypto miners BH Miner and BH Miners Box. These miners have been built around ...
Semiconductor Engineering

Adding NoCs To FPGA SoCs

FPGA SoCs straddle the line between flexibility and performance by combining elements of both FPGAs and ASICs. But as they find a home in more safety- and mission-critical markets, they also are ...
Electronic Design

ASICs, Structured ASICs, And FPGAs

How close in performance and integration are FPGAs and ASICs? Advances in FPGA architectures and the use of 90-nm process rules have allowed the latest generation of FPGAs to achieve levels of ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Design-Reuse

M2000 starts offering IP cores and tools that marry ASIC and FPGA design

San Jose, Calif. - More than a few chip companies have tried their hand at embedding blocks of FPGA logic into otherwise-hardwired ASIC devices. Startup M2000 says it wants to be the first to make a ...
Design News

Is Platypus from Zero ASIC the FPGA equivalent to RISC-V?

Before I tell you what I’m about to tell you, let’s first refresh our minds as to RISC-V processors. Why? Well, because even though what I’m about to tell you has nothing to do with RISC-V per se, in ...