EDN

Making biometrics the killer app of FPGA dynamic partial reconfiguration

Editor’s Note: This article is reproduced from the Xilinx Xcell Journal with the kind permission of the folks from Xilinx. In the current era of communications and information technologies, automatic ...
Design-Reuse

Partial reconfiguration in FPGA rapid prototyping tools

FPGA rapid prototyping tools are greatly useful at the time of designing and testing complex signal processing systems, due to their graphic programming environment and the possibility they offer to ...
Design-Reuse

An MDE Approach For Implementing Partial Dynamic Reconfiguration In FPGAs

Field programmable gate arrays (FPGAs) provide an interesting solution when custom logic is needed for short time to market products. The products embedding FPGA System on chip solutions allow them to ...
EDN

Xilinx Improves Design Flow for Industry’s Only Proven Partial Reconfiguration FPGA Technology with ISE Design Suite 12.2

SAN JOSE, Calif., July 27 /PRNewswire/ –Xilinx, Inc. (Nasdaq: XLNX) today announced the availability of its fourth generation partial reconfiguration design flow and new improvements to its ...