EDN

Design of High Speed Pipelined 16 bit Adder

1)Programming Languages: Verilog HDL, VHDL, C, C++, TCL scripting, HTML 2)Operating Systems: Windows, Unix and Mac operating systems 3)EDA Tools: Cadence - Virtuoso ...
EDN

Design of Adder

In divide & conquer approach the 16 bit number is divided into individual 8 bits. If we continue to divide we reach the leaf level of the problem. In the leaf level of the D&C Tree is a 1 bit adder, ...
TechRepublic

Design of High Performance 16-Bit Brent Kung Adder Using Static CMOS Logic Style in 45nm CMOS NCSU Free PDK

High performance microprocessor units require high performance adders and other arithmetic units. Modern microprocessors are however 32-bits or 64-bits as that is the minimum required for floating ...
TechRepublic

Design and Implementation of 16-Bit Magnitude Comparator Using Efficient Low Power High Performance Full Adders

In VLSI applications, area, delay and power are the important factors which must be taken into account in the design of a fast adder. The paper attempts to examine the features of certain adder ...