LONDON — Tiempo AS (Grenoble, France) has said it will demonstrate the first synthesis tool for asynchronous logic that operates from standard design languages at the Design Automation Conference, due ...

Asynchronous processors, which function without a global clock, have emerged as a compelling alternative to traditional synchronous architectures. Their design relies on handshake protocols and local ...

Wire delay is beginning to dominate gate delay in current CMOS technologies. According to Moore’s Law by 2016 CMOS feature size should be on the order of 22 nm with clock frequencies reaching around ...